In today's integrated circuit technology it is desirable to obtain linewidths in the range of about 0.5 .mu.m by using standard photolithography techniques, and to avoid the application of more complex techniques such as E-beam or X-ray lithography. Recently, there has been significant effort in the integrated circuit field to develop processes for making submicrometer channel length field effect transistors with a high degree of channel length control. Examples of this work are described in U.S. Pat. Nos. 4,209,349, filed on Nov. 3, 1978, by I. T. Ho et al, 4,209,350, filed on Nov. 3, 1978, by I. T. Ho et al, 4,234,362, filed on Nov. 3, 1978, by J. Riseman, 4,256,514, filed on Nov. 3, 1978, by H. B. Pogge, and 4,502,914, filed on Oct. 28, 1983, by H. J. Trumpp et al. These patents all involve the formation of substantially horizontal surfaces and substantially vertical surfaces on a silicon body, and then forming a layer of a very narrow dimension on both the substantially horizontal and substantially vertical surfaces. This layer is then subjected to an anisotropic etching process such as by reactive ion etching, to substantially remove the horizontal layer while leaving the vertical layer substantially intact. The vertical layer dimension is adjusted depending on the original thickness of the layer applied. In this way a narrow dimension region such as a field effect transistor gate of submicrometer length can be obtained.
Another approach uses a tri-layer resist system to define the gate electrode of a field effect transistor by photo or E-beam lithography. In this process (see for example PCT Application No. WO-A-80/00639) a comparatively thick bottom polymer or resist layer is deposited on the surface of a polycrystalline silicon layer which is designated to be in part the gate electrode. After a baking step an intermediate barrier layer of silicon dioxide or nitride is deposited by chemical vapor deposition at room temperature. The top layer is a highly sensitive positive photoresist layer in which the desired pattern of the gate electrode is generated by optical or E-beam exposure and development. Pattern transfer from the top resist to the silicon dioxide or nitride barrier layer is achieved by plasma etching with carbon tetrafluoride (CF.sub.4). An oxygen reactive ion etch (RIE) process is used to transfer the pattern to the bottom polymer or resist layer. According to this approach the bottom resist layer is oxygen etched at a relatively high pressure for obtaining lateral bias etching of the silicon dioxide/nitride barrier layer by a particular amount. The resulting bottom layer photoresist bars, decreased by the line width bias over the original line width of the top resist layer, serve as a photoresist mask for the subsequent polycrystalline silicon RIE step. This step has poor dimensional control as it is known that the base of the photoresist bars is not exactly defined and differs in width to a considerable extent from the wafer center to the edge. In addition, due to the overhanging oxide or nitride, the lateral oxygen etch rate is not constant with respect to time, and the average line width bias is limited by the geometry.